1. Field of the Invention
The present invention relates to a memory module including a multiplicity of memory devices such as SDRAMs (Synchronous Dynamic Random Access Memories) formed on a substrate.
2. Description of the Background Art
FIG. 13 shows a background art memory module. The memory module MMc of FIG. 13 comprises eight memory devices MD0 to MD7 formed on a memory module substrate. A memory device, as that term is used herein, is a storage element in the form of a chip. As an example, eight data lines DQ0 to DQ7 are connected to the memory device MD0, and data lines DQ8 to DQ15 are connected to the memory device MD1. Likewise, data lines are connected to each of the other memory devices MD2 to MD7. The data lines DQ0 to DQ63 serve as transmission paths for transmitting and receiving data to and from a portion external to the memory module MMc during a memory operation such as bit-wise writing and reading of data into and from a memory cell in each of the memory devices MD0 to MD7 and a refresh operation. The memory devices MD0 to MD7 are also connected to signal lines, not shown, for transmitting operating signals such as a write enable signal and an address signal for the memory operation in addition to the data lines DQ0 to DQ63.
Thus, the memory module has such a large number of signal lines for connection to the memory devices, and these signal lines are connected to the external portion through I/O pins provided on the memory module substrate.
Memory modules, after being manufactured, are generally inspected by some tests such as an electrical assembly check for judging whether or not interconnect lines are formed well, a data write and read operation test, and a memory content retention operation check.
However, the increased number of I/O pins of the memory module as above described has required an expensive tester having a great number of I/O pins even when the electrical assembly check and the simple data write and read operation test (e.g., a write operation which applies xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d to all data lines and a subsequent read operation) are performed. The tester having a great number of I/O pins is expensive since the tester includes a data write driver and a data read comparator for each of the I/O pins.
Thus, there arises a need for a memory module which allows an inexpensive tester to carry out the electrical assembly check and the simple data write and read operation test on the memory devices.
A technique for conducting the above described tests on a single memory device, rather than the memory module, is disclosed in, for example, Japanese Patent Application Laid-Open Nos. P61-261895A and P61-292300A (1986).
FIG. 14 shows a technique disclosed in Japanese Patent Application Laid-Open No. P61-261895A. In this technique, data lines 111 establish connection between a memory array 101 and a multiplexer 102, and data from the memory array 101 is outputted through the multiplexer 102. An output from the multiplexer 102 is outputted through a switching circuit 103 for switching between the memory operation and a testing operation, an output buffer 104 and an output pad 105 to an external portion. An exclusive OR circuit 106 is also connected to the memory array 101 through data lines 112. The exclusive OR circuit 106 conducts tests on the memory array 101.
Operation in this technique is described below. In the memory operation, a signal xcfx861 inputted to the switching circuit 103 is xe2x80x9c0,xe2x80x9d and the output from the multiplexer 102 is applied to the output buffer 104 independently of an output from the exclusive OR circuit 106.
In the testing operation, on the other hand, the signal xcfx861 inputted to the switching circuit 103 is xe2x80x9c1.xe2x80x9d The same 1-bit data (e.g., xe2x80x9c1xe2x80x9d) is written into all memory cells to be tested in the memory array 101. The exclusive OR circuit 106 receives a 1-bit data signal xcfx862 which is the same as the data written into the memory array 101 and outputs from the data lines 112 to perform an exclusive OR operation thereon.
In the event of imperfect interconnect formation or a data read and write malfunction in the memory array 101, there is a high possibility that data other than xe2x80x9c1xe2x80x9d appears on one of the data lines 112. Therefore, the memory array 101 is judged as being normal when the output from the exclusive OR circuit 106 is xe2x80x9c0,xe2x80x9d i.e., all inputs to the exclusive OR circuit 106 are the same 1-bit data. On the other hand, the memory array 101 is judged as being defective when the output from the exclusive OR circuit 106 is xe2x80x9c1.xe2x80x9d In this manner, whether the memory device is good or not is examined.
The use of this technique allows an inexpensive tester including a single comparator to conduct the electrical assembly check and the simple data write and read operation test on the memory device.
This technique may be applied to a memory module to accomplish the memory module on which an inexpensive tester can conduct the above described tests. Specifically, the memory device shown in FIG. 14 may be used as a device to be mounted in the memory module.
However, simply mounting this memory device into the memory module is not sufficient, but it is necessary that output signals TMS0 to TMS7 are outputted from the memory devices MD0 to MD7, respectively, as in a memory module MMd shown in FIG. 15, for example. Thus, there is a limit to the use of an inexpensive tester having a smaller number of I/O pins.
Additionally, a testing circuit provided in a memory device as in the above described technique is not always capable of conducting perfect tests since, in some tests, the signals from the memory array 101 bypass a circuit through which those signals pass during the memory operation. For instance, since the multiplexer 102 is bypassed during the testing operation in the arrangement shown in FIG. 14, it is impossible to test the entire device including the operation of the multiplexer 102.
Further, the direct connection of the exclusive OR circuit 106 to test to the memory array 101 as in the memory device shown in FIG. 14 causes an input load of the exclusive OR circuit 106 to be imposed on the memory array 101 during the memory operation, thereby requiring an additional driving capability when the memory array 101 outputs data. Moreover, signal reflection is prone to occur on the data lines 111, resulting in deterioration of data I/O characteristics.
The provision of the testing circuit in the memory device presents another problem of increasing the chip size of the memory device itself, resulting in increased costs.
The technique disclosed in Japanese Patent Application Laid-Open No. P61-292300A (1986) has similar problems.
According to a first aspect of the present invention, a memory module comprises: at least one memory device connected to at least one data line for bit-wise transmitting and receiving data to and from an external portion; an exclusive OR element having at least one input corresponding to the at least one data line; and at least one switch for connecting the at least one data line to the external portion and the at least one input of the exclusive OR element, wherein the at least one switch receives a first instruction for causing the at least one switch to connect the at least one data line to the at least one input of the exclusive OR element in a testing operation and causing the at least one switch to connect the at least one data line to the external portion in a memory operation.
Preferably, according to a second aspect of the present invention, in the memory module of the first aspect, in the testing operation, common 1-bit data is applied to the at least one data line and stored in the at least one memory device before the first instruction causes the at least one switch to connect the at least one data line to the at least one input of the exclusive OR element, and thereafter whether the at least one memory device malfunctions or not is judged by checking an output from the exclusive OR element.
Preferably, according to a third aspect of the present invention, in the memory module of the first aspect, at least one memory device includes a plurality of memory devices; and the exclusive OR element and the at least one switch are provided in corresponding relation to each of the plurality of memory devices.
Preferably, according to a fourth aspect of the present invention, in the memory module of the first or third aspect, the at least one switch further connects the at least one input of the exclusive OR element to a fixed potential in the memory operation.
Preferably, according to a fifth aspect of the present invention, in the memory module of the first or third aspect, an operating signal for controlling the at least one memory device is inputted from the external portion to the at least one memory device; and the at least one memory device performs the memory operation when the operating signal is in a pre-defined significant condition. The memory module further comprises control means for providing the first instruction to the at least one switch, the control means placing the at least one switch into a condition achieved in the testing operation when the operating signal is in a predetermined condition other than the significant condition.
Preferably, according to a sixth aspect of the present invention, in the memory module of the fifth aspect, the operating signal includes a plurality of operating signals; and the control means places the at least one switch into the condition achieved in the testing operation when a predetermined one of combinations of the plurality of operating signals which does not contribute to the memory operation is inputted to the control means.
Preferably, according to a seventh aspect of the present invention, in the memory module of the first or third aspect, the exclusive OR element further has another input capable of receiving arbitrary 1-bit data.
Preferably, according to an eighth aspect of the present invention, in the memory module of the first or third aspect, an operating signal for selecting the at least one memory device is inputted from the external portion to the at least one memory device; and an unselected one of the at least one memory device provides a second instruction to the at least one switch to prevent the at least one data line from being connected to the external portion.
Preferably, according to a ninth aspect of the present invention, the memory module of the eighth aspect further comprises an OR element receiving the first and second instructions, wherein the at least one switch is controlled by an output from the OR element.
According to a tenth aspect of the present invention, a memory module comprises: a memory device; and control means, wherein an operating signal for controlling the memory device is inputted from an external portion to the memory device; wherein the memory device performs a memory operation when the operating signal is in a pre-defined significant condition; and wherein the control means outputs a signal regarding a predetermined operation differing from the memory operation when the operating signal is in a predetermined condition other than the significant condition.
Preferably, according to an eleventh aspect of the present invention, in the memory module of the tenth aspect, the operating signal includes a plurality of operating signals; and the control means outputs the signal regarding the predetermined operation when a predetermined one of combinations of the plurality of operating signals which does not contribute to the memory operation is inputted to the control means.
In accordance with the first aspect of the present invention, the at least one switch connects the at least one data line to the at least one input of the exclusive OR element in the testing operation, and connects the at least one data line to the external portion in the memory operation. Therefore, in the testing operation, an electrical assembly check and a simple data write and read operation test may be conducted on the at least one memory device by observing the output from the exclusive OR element. In the memory operation, since the at least one input of the exclusive OR element is not connected to the at least one data line, an additional load is not imposed on the at least one data line, and signal reflection does not occur on the at least one data line.
In accordance with the second aspect of the present invention, in the testing operation, whether the at least one memory device malfunctions or not is judged by checking the output from the exclusive OR element after the common 1-bit data is applied to the at least one data line and stored in the at least one memory device. Therefore, the electrical assembly check and the simple data write and read operation test may be easily conducted on the at least one memory device.
In accordance with the third aspect of the present invention, the exclusive OR element and the at least one switch are provided in corresponding relation to each of the plurality of memory devices. Therefore, which memory device malfunctions is determined.
In accordance with the fourth aspect of the present invention, the at least one switch further connects the at least one input of the exclusive OR element to the fixed potential in the memory operation. This suppresses power consumption resulting from a stray capacitance and noise at the at least one input of the exclusive OR element.
In accordance with the fifth aspect of the present invention, the control means provides the first instruction to the at least one switch, and places the at least one switch into the condition achieved in the testing operation when the operating signal is in the predetermined condition other than the significant condition. This eliminates the need for the memory module to include an additional input pin for the first instruction, and also reduces the number of interconnect lines of a system board to which the memory module is to be connected.
In accordance with the sixth aspect of the present invention, the at least one switch is placed into the condition achieved in the testing operation when a predetermined one of combinations of the plurality of operating signals which does not contribute to the memory operation is inputted. This permits effective use of the predetermined combination of the operating signals which does not contribute to the memory operation.
In accordance with the seventh aspect of the present invention, the exclusive OR element further has the additional input capable of receiving the arbitrary 1-bit data. Thus, the at least one memory device may be tested for malfunction, based on whether or not the output from the at least one data line coincides with the arbitrary 1-bit data applied to the additional input even in the event of a malfunction such that the output from every one of the at least one data line is inverted.
In accordance with the eighth aspect of the present invention, an unselected one of the at least one memory device provides the second instruction to the at least one switch to prevent the at least one data line from being connected to the external portion. There is no need to additionally provide a separate bus switch.
In accordance with the ninth aspect of the present invention, the at least one switch is controlled by the output from the OR element which receives the first and second instructions. Therefore, the at least one switch is required to receive only the single instruction.
In accordance with the tenth aspect of the present invention, the control means outputs the signal regarding the predetermined operation differing from the memory operation when the operating signal is in the predetermined condition other than the significant condition. This eliminates the need for the memory module to include an additional pin for input of the signal regarding the predetermined operation, and also reduces the number of interconnect lines of a system board to which the memory module is to be connected.
In accordance with the eleventh aspect of the present invention, the control means outputs the signal regarding the predetermined operation when a predetermined one of combinations of the plurality of operating signals which does not contribute to the memory operation is inputted to the control means. This permits effective use of the predetermined combination of the operating signals which does not contribute to the memory operation.
It is therefore an object of the present invention to provide a memory module Which allows an inexpensive tester to conduct an electrical assembly check and a simple data write and read operation test upon memory devices thereof, which includes a smaller number of I/O pins for the check and test, and which does not deteriorate data input/output characteristics of the memory devices.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.